1. Field of the Invention
This invention relates to monolithic linear integrated circuits, and in particular, to linear integrated circuits wherein the input-stage transistor has both high gain and high breakdown voltage characteristics.
2. Description of the Prior Art
Monolithic integrated circuits useful for linear applications, such as operational amplifiers, should have an input-stage transistor with a relatively high forward-current transfer ratio, for example, above 1,000. As known in the art, the forward-current transfer ratio is the ratio of the output collector current to the input base current, and is referred to as the gain, or beta. The gain of a transistor is inversely proportional to the distance between its emitter-base PN junction and its collector-base PN junction, that is, the shorter the distance between the two PN junctions, the higher the gain. The gain also is inversely proportional to the charge density of the base region, that is, the lower the quantity of dopant atoms per cubic centimeter of P-type or N-type conductivity in the base region, the higher the gain, particularly in the active portion of the base between the emitter-base and collector-base PN junctions.
In addition, the input-stage transistor should have a relatively high breakdown voltage level, that is, the level of reverse-bias voltage required to cause breakdown to occur between the collector and emitter should be on the order of 40 to 45 volts.
Previously, it has been difficult, using standard semiconductor processing techniques, to fabricate transistors in linear integrated circuits that had both high gain and high emitter-collector breakdown voltage. It has also been difficult to fabricate linear integrated circuits in which one transistor had high gain but moderate breakdown voltage, such as about 10 volts, and another transistor had high breakdown voltage but moderate gain, such as above 150. Accordingly, compromises have had to be made, so that for many linear integrated circuits, at least two transistors are required, one to provide high gain at the input-stage, and the other to provide high breakdown voltage at the intermediate stages or at the output-stage, but with the high-gain transistor having low breakdown voltage, such as about 1.5 to 2 volts, and the high breakdown voltage transistor having low gain, such as about 50 to 150.
A prior-art method of fabricating a linear integrated circuit with at least two transistors of differing electrical characteristics comprises forming the high-gain input-stage transistor so that the distance between its collector-base and emitter-base PN junctions is relatively short, that is, not more than about three tenths of a micron, which is at least one-half of the typical distance between the two PN junctions of other transistors in the integrated circuit, a distance that usually varies from six tenths to one micron. The relatively short distance between the two PN junctions provides a relatively high gain, for example, in the range of 1,500 to 10,000, but the breakdown voltage between the two junctions, also referred to as the reach-through, or punch-through voltage, is undesirably low, such as about 1.5 to 2 volts, because the two junctions are so close together. A reach-through or punch-through effect occurs between two PN junctions when enough reverse-bias voltage is applied to one of the junctions to cause the latter to spread and electrically contact either the adjacent PN junction or an interconnection contact, resulting in a short circuit between the two PN junctions or between the spreading PN junction and the interconnection contact. The shorter the distance between junctions, the easier it is for one or both of them to spread and electrically contact each other.
Moreover, a very short distance between adjacent PN junctions in prior-art high-gain transistors causes fabrication difficulties using standard semiconductor processing techniques, because it is difficult to control easily the exact distance between the two PN junctions as the junctions are being formed. The collector, base, and emitter regions of a transistor are typically created by the diffusion of dopant atoms of N-type or P-type conductivity into a substrate of semiconductor material, wherein the concentration of the dopant atoms and the depth of the region are a function of the heat applied to cause the diffusion and the time period during which the diffusion occurs; when the distance between adjacent PN junctions has to be not more than three tenths of a micron. such a short distance makes it difficult to control accurately the exact depth of a PN junction and the distance between adjacent PN junctions. Consequently, with large-scale fabrication of numerous semiconductor devices on a wafer of semiconductor material. wide variations can occur in the electrical characteristics between devices. These wide variations substantially reduce the manufacturing yield and increase the production cost.
Typically, a second transistor, that is, one with high breakdown voltage, is formed on the substrate adjacent to the first, or high-gain, transistor. As mentioned above, the distance between the collector-base and emitter-base PN junctions of the second transistor is about six tenths to 1 micron. The longer distance between PN junctions provides a much higher collector-emitter breakdown voltage, such as about 40 to 45 volts, but the gain is relatively low to moderate, such as from 100 to 400. The two-transistor structure provides a compromise between the need for high gain and need for high breakdown voltage, but yield can be relatively low and manufacturing cost high because of problems in controlling the exact distance between adjacent PN junctions in the high-gain transistor when the distance cannot exceed three tenths of a micron.
In order to overcome some of the above-mentioned problems while fabricating an input-stage transistor with high gain, an alternative approach is used. In this approach, the base region is formed so that the charge density of dopant atoms therein is relatively low, such as about 10.sup.17 dopant atoms per cubic centimeter, which is about an order of magnitude less than the typical charge density of a base region. A base region with a low charge density means that the gain of the transistor is substantially increased. Moreover, the distance between the emitter-base and collector-base PN junctions of the transistor are not less than six tenths to 1 micron, so that the collector-emitter breakdown voltage is higher. However, when the base region has a low charge density, voltage potentials in the interconnect leads atop the passivation layer over the principal surface, for example, in the range of 20 to 40 volts, create an inversion layer along the upper surface portion of the base region. Such an inversion layer can cause a short circuit between the emitter and collector regions. Therefore, the alternative approach of using a base region with a low charge density is often undesirable because of the inversion layer problem.
A need thus exists for an improved monolithic integrated circuit structure useful for linear applications, such as an operational amplifier, wherein the transistor for the input-stage has both high gain and high breakdown voltage. The structure should be compatible with mass production semiconductor processing techniques and allow high yield with reduced cost as well as ensure consistent electrical characteristics between devices. In addition, the structure should prevent unwanted field inversion layers occurring along the surface of the base. Furthermore, the structure should eliminate the necessity of having two transistors, one for high gain and the other for high breakdown voltage.